1. Field of the Invention
The present invention relates to a structure of a dynamic frequency divider.
2. Description of the Related Art
Frequency Divider (FD) is an important building block which is widely used in logic systems and transmission systems, including phase locked loop (PLL), Clock Multiplication Unit (CMU), and clock generators (CkGen). The master-slave Toggle flip-flop (TFF) configuration is one of the most common types used in both dynamic and static frequency dividers. However, propagation delays of logic gates and switches in the TFF limits the maximum operation frequency. Especially in CMOS and BiCMOS processes, there is not yet a high enough operating frequency range for high data rate applications like the 40 Gbps transmission systems.
FIGS. 1 through 4 depict the conventional frequency divider.
A conventional FD (conv. FD1) uses master-slave buffer elements, but the highest operation frequency is limited. Another conventional FD (conv. FD2) uses an analog mixer (or analog multiplier), but the circuit configuration cannot operate very fast if standard CMOS process is used.
Circuit shown in FIG. 1 is a conventional frequency divider (FD1) with two switches sw1 and sw2 that are alternatively controlled by an input clock signal (CK). In some articles, the frequency divider is called an edge-triggered master/slave Toggle flip-flop (TFF). The same clock is used to drive both level-triggered TFF with opposite logic.
The operation of FD1 is mainly determined by shuffling the voltage level of CK signal, activating only one buffer, 10 or 11, at the same moment, while another buffer holds the voltage level in the previous CK period. The inverted output by the inverter 12 is fed back to the input port “outb”. (In other words, the inverter 12 is to invert “out” value such that “out” will change its value in the next period.) The first buffer 10 is commonly called the master buffer and the second one 11 is normally referred to as the slave buffer. Either the master buffer 10 or the slave buffer 11 is activated in each half-clock cycle, ensuring that not both buffers will change their output values at the same time (because of the switches between them). As shown in FIG. 2, “out” will change its value once while CK changes from 1 to 0. In other words, the output clock signal “out” is a frequency that is half that of “CK”.
As shown in the timing diagram in FIG. 2, there is time restriction to the above circuit such that T(CK=1) should be larger than (t_sw+t_buf), and T(CK=0) should be larger than (t_sw+t_buf+t_inv). Wherein t_sw is a delay time of switches sw1 and sw2, t_buf is a delay time of buffers 10 and 11 and t_inv is a delay time of the inverter 12. As a result, the maximum frequency must be less than 1/(2*(t_sw+t_buf)+t_inv). The input clock frequency cannot be higher than this value. Otherwise, the outputs (k′ and out) do not have enough time to toggle, and the output will be stuck to the initial value or the value in the previous CK period.
FIG. 3 shows another conventional FD, conventional FD2, which contains a mixer/multiplier 15, a low pass filter (LPF) 16 and an amplifier (AMP) 17. Frequency values of the input CK signal, output of the mixer/multiplier 15, output of the LPF 16, and output of the conventional FD2 are denoted by fc, fc±fo, fc−fo, and fo, respectively. In this circuit, an analog mixer, or multiplier 15, is used to modulate the input CK with the output such that mixer's output contains frequency harmonics of (fc+fo) and (fc−fo). By using the LPF 16, only the lower harmonic (fc−fo) is passed to the AMP 17, which amplifies the signal as output.
The stable condition (or lock condition) of this circuit can be expressed byfo=fc−fo  equation (1),
where fc is frequency of input CK, and fo is frequency of output of the FD.
The above equation implies thatfo=fc/2  equation (2),which indicates function of a frequency divider (The above circuit is called “Miller divider” in some articles.).
An example of implementation of this circuit is shown in FIG. 4, in which GaAs bipolar transistors are used. All signal paths, including internal nodes, are in differential mode, such that there are {fc, fcb} at the clock input and {fo, fob} at the output, where fcb is a negation of fc and fob is a negation of fo. Firstly, the differential inputs {fc, fcb} are connected to two resistors 20 and 21, which are part of a DC biasing circuit. This biasing circuit adjusts {fc, fcb}'s voltage to a suitable level for the high speed mixer (or “Gilbert” multiplier) 22. This FD can achieve high frequency operation due to the high performance of the “Gilbert” style multiplier 22. The parasitic capacitances at nodes “x” and “y” (resulting from collector nodes of Q3-Q6 and base nodes of Q7-Q8), along with load resistors (Rx and Ry), form the low pass filter. The three cascaded emitter followers 23 further perform amplification and wave-shaping. “fo” and “fob” are fed back to transistors Q1 and Q2, respectively. High speed operation of this FD comes from that high speed mixer and high gain amplifier and can be implemented readily with bipolar transistors such that this circuit can operate at high frequency “Input CK”. If standard CMOS process is used, such configuration is difficult to design, and high speed operation cannot be achieved.
The input frequency at “Input” can be as high as f_miller=1/(Rx*Cx), where Cx is the total parasitic capacitance at node “x”, and Rx is the resistance value of RX. For typical bipolar circuits, typical values of Cx and Rx are 0.50 pF and 50 ohm, respectively. Thus, the f_miller value of bipolar implementation is 40 GHz. However, for a typical CMOS circuit, typical values of Cx and Rx are 1.00 pF and 200 ohm, respectively. (The higher value of Rx is necessary to maintain adequate gain of the “Gilbert” multiplier.) Thus, the f_miller value of CMOS implementation is 5 GHz.
In the application of compact transmission systems or portable terminals, power consumption becomes an important concern such that CMOS LSI is often preferred. In cases of high data rate applications like 40 Gbps transmission systems, a FD which operates at 20 GHz is required. If the FD is implemented in standard CMOS process, both the power consumption and the fabrication cost can be lowered.
The total internal propagation delay is large in conventional master-slave type frequency divider (FD) such that maximum operating frequency is limited. On the other hand, high speed frequency dividers consume high power if fabricated with bipolar transistors and high frequency is difficult to achieve when using standard CMOS process.